Avalanche Technology, Inc.
Patent Owner
Stats
- 243 US PATENTS IN FORCE
- 6 US APPLICATIONS PENDING
- Mar 20, 2018 most recent publication
Details
- 243 Issued Patents
- 0 Issued in last 3 years
- 0 Published in last 3 years
- 6,251 Total Citation Count
- Feb 12, 2007 Earliest Filing
- 33 Expired/Abandoned/Withdrawn Patents
Patent Activity in the Last 10 Years
Technologies
Intl Class
Technology
Matters
Rank in Class
Top Patents (by citation)
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Recent Publications
Publication #
Title
Filing Date
Pub Date
Intl Class
2017/0249,161 Method of Implementing Magnetic Random Access Memory (MRAM) for Mobile System-on-Chip BootMay 11, 17Aug 31, 17[G06F, G11C]
2017/0220,301 Memory Device for Emulating Dynamic Random Access Memory (DRAM)Jan 29, 16Aug 03, 17[G06F, G11C]
2017/0162,242 Method and Apparatus for Adjustment of Current Through a Magnetoresistive Tunnel Junction (MTJ) Based on Temperature FluctuationsFeb 16, 17Jun 08, 17[G11C]
2015/0311,252 MAGNETIC RANDOM ACCESS MEMORY WITH ULTRATHIN REFERENCE LAYERApr 28, 14Oct 29, 15[H01L]
2015/0311,431 MAGNETIC RANDOM ACCESS MEMORY WITH ULTRATHIN REFERENCE LAYERJun 03, 15Oct 29, 15[H01L]
Recent Patents
Patent #
Title
Filing Date
Issue Date
Intl Class
9921782 Memory device for emulating dynamic Random access memory (DRAM)Jan 29, 16Mar 20, 18[G06F, G11C]
9911482 Method and apparatus for adjustment of current through a magnetoresistive tunnel junction (MTJ) based on temperature fluctuationsFeb 16, 17Mar 06, 18[G11C]
9898204 Magnetic random access memory with dynamic random access memory (DRAM)-like interfaceMay 19, 17Feb 20, 18[G06F, G11C]
9871190 Magnetic random access memory with ultrathin reference layerApr 28, 14Jan 16, 18[H01L, G11C]
9871191 Magnetic random access memory with ultrathin reference layerJun 03, 15Jan 16, 18[H01L, G11C]
9858977 Programming of magnetic random access memory (MRAM) by boosting gate voltageAug 28, 17Jan 02, 18[G11C]
9830106 Management of memory array with magnetic random access memory (MRAM)Jan 20, 17Nov 28, 17[G06F, G11C]
9831421 Magnetic memory element with composite fixed layerJul 13, 15Nov 28, 17[H01L, B82Y, H01F, G11C]
9824050 Shared PCIe end point system including a PCIe switch and method for initializing the switchNov 20, 15Nov 21, 17[G06F]
9812499 Memory device incorporating selector element with multiple thresholdsJul 27, 16Nov 07, 17[H01L]
Expired/Abandoned/Withdrawn Patents
Patent #
Title
Status
Filing Date
Issue/Pub Date
Intl Class
2017/0091,021 Reduction of Area and Power for Sense Amplifier in MemoryAbandonedSep 26, 16Mar 30, 17[G06F, G11C]
2016/0085,708 MULTI-LEVEL SCALABLE SWITCH ARCHITECTURE FOR STORAGE APPLIANCEAbandonedSep 01, 15Mar 24, 16[G06F]
2016/0088,772 METHOD AND APPARATUS TO REDUCE THERMAL RESISTANCE IN A SERVER CHASSISAbandonedSep 03, 15Mar 24, 16[H05K]
2015/0378,884 STORAGE SYSTEM CONTROLLING ADDRESSING OF SOLID STORAGE DISKS (SSD)AbandonedApr 06, 15Dec 31, 15[G06F]
2015/0316,971 METHOD AND APPARATUS TO REDUCE POWER CONSUMPTION OF MOBILE AND PORTABLE DEVICES WITH NON-VOLATILE MEMORIESAbandonedMay 02, 14Nov 05, 15[G06F]
2015/0248,346 PHYSICALLY-ADDRESSABLE SOLID STATE DISK (SSD) AND A METHOD OF ADDRESSING THE SAMEAbandonedApr 27, 15Sep 03, 15[G06F, G11C]
2015/0212,752 STORAGE SYSTEM REDUNDANT ARRAY OF SOLID STATE DISK ARRAYAbandonedApr 03, 15Jul 30, 15[G06F]
2015/0212,755 METHOD OF MANAGING THROUGHPUT OF REDUNDANT ARRAY OF INDEPENDENT DISKS (RAID) GROUPS IN A SOLID STATE DISK ARRAYAbandonedJan 30, 14Jul 30, 15[G06F]
2015/0199,152 METHOD OF MANAGING REDUNDANT ARRAY OF INDEPENDENT DISKS (RAID) GROUPS IN A SOLID STATE DISK ARRAYAbandonedJan 16, 14Jul 16, 15[G06F]
2015/0194,598 PERPENDICULAR STTMRAM DEVICE WITH BALANCED REFERENCE LAYERAbandonedMar 18, 15Jul 09, 15[H01L]
2015/0095,555 METHOD OF THIN PROVISIONING IN A SOLID STATE DISK ARRAYAbandonedFeb 03, 14Apr 02, 15[G06F]
2015/0074,347 SECURE SPIN TORQUE TRANSFER MAGNETIC RANDOM ACCESS MEMORY (STTMRAM)AbandonedNov 14, 14Mar 12, 15[H04L, G06F, G11C]
2015/0014,800 MTJ MEMORY CELL WITH PROTECTION SLEEVE AND METHOD FOR MAKING SAMEAbandonedSep 30, 14Jan 15, 15[H01L, G11C]
2014/0281,680 DUAL DATA RATE BRIDGE CONTROLLER WITH ONE-STEP MAJORITY LOGIC DECODABLE CODES FOR MULTIPLE BIT ERROR CORRECTIONS WITH LOW LATENCYAbandonedMar 17, 14Sep 18, 14[G06F]
2014/0143,480 MANAGEMENT OF MEMORY ARRAY WITH MAGNETIC RANDOM ACCESS MEMORY (MRAM)AbandonedNov 26, 13May 22, 14[G06F]
2014/0047,161 System Employing MRAM and Physically Addressed Solid State DiskAbandonedNov 09, 12Feb 13, 14[G06F]
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